This invention relates to phase-locked loop circuitry provided in one portion of a programmable logic device, where the phase-locked loop circuitry can be used in another portion of the programmable logic device.
It is known to incorporate phase-locked loop (“PLL”) circuitry on programmable logic devices (“PLDs”). For example, it has become common for PLDs to accommodate various input/output (“I/O”) standards, some of which require very accurate high-speed clocks. One way of providing such clocks is to provide PLL circuitry on the PLD.
For example, recently PLDs have begun to incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) high-speed serial I/O standards—e.g., the XAUI (10 Gbps Extended Attachment Unit Interface) standard. In accordance with the XAUI standard, a high-speed serial interface includes transceiver groups known as “quads,” each of which includes four transceivers and some central logic. Within each transceiver, the receiver portion typically includes a PLL, primarily for the purpose of enabling clock data recovery from a received high-speed serial signal. In addition, the central logic typically includes a PLL, primarily for the purpose of generating a transmit clock to be used by the transmitter portion of each of the four transceivers. Thus, a quad typically includes five PLLs.
PLLs are relatively large and complex circuits, and providing PLLs on PLDs therefore either adds significant area to the PLD, or takes away area that could be used for programmable logic circuitry in a PLD of a given size. Because PLDs are, by definition, programmable by their users, in any particular user logic design for a PLD including a high-speed serial interface as described above, there is a significant probability that some or all of the PLLs included in that interface may not be used in the user logic design. As far as that user design is concerned, the PLL circuitry is simply wasted. It would be desirable to be able to recapture that circuitry when it is not being used as part of the high-speed serial interface.